The present invention relates generally to first in first out storage devices (FIFOs) and, more particularly, to a FIFO apparatus and method wherein no changes occur on an output thereof in response to (1) only one stage of the FIFO having a signal stored therein when a read command is supplied to the FIFO exclusively of a write command and/or (2) the FIFO being flushed, i.e., the contents thereof being effectively erased.
First in first out storage devices (FIFOs) include a signal input, a signal output and multiple (N) stages between the input and output. The stages respond to the input such that a signal supplied first in time to the input is derived first in time at the output. Writing and reading of synchronous FIFOs is in response to an edge of clock pulses. Usually, FIFOs are responsive to multibit words so each of the N storage stages has n bits, where n is equal to the number of bits in a word.
One type of prior art synchronous FIFO uses a shift register structure in which signals propagate through a register bank having storage elements or stages serially connected together. The bits of a first word are shifted into a first element, thence to further elements of the register bank and are derived at the output after N clock pulses have been supplied to the register bank. This type of FIFO does not require complex control and is adequate for relatively low values of N or where the latency of data supplied to the FIFO relative to the data derived at the FIFO output is not important.
Most modern synchronous FIFOs, however, use a random access memory (RAM) structure and control logic employing write and read pointers or enable bits for each word, as well as an entry counter. The write and read pointers route signals from the input to appropriate static memory stages in the RAM, thence to the FIFO output. The signals are supplied to the stages under the control of the write pointer and are coupled from the stages to the output terminal under the control of the read pointer. The entry counter keeps track of the number of stages in the RAM memory having signals stored therein. Control logic of such FIFOs indicates the state of the RAM and where signals are located in the RAM.
In most RAM based FIFOs, reading the last entry from the FIFO advances the FIFO to an empty state, i.e., such that no signals are stored in any of the FIFO stages. In advancing the FIFO to the empty state, redundant signal transitions are derived at the output, usually a data bus having n bits. The redundant transitions are derived because the control logic for the read and write pointers is usually designed such that all write commands advance the write pointer and all read commands advance the read pointer. Hence, the read command which advances the read pointer to render the FIFO empty causes transitions to be derived at the FIFO output. These transitions which occur when the FIFO is being emptied cause a considerable amount of power to be consumed in the FIFO, as well as in components responsive to the FIFO output. This power consumption, which I have realized is unnecessary, has an adverse effect on the length of time a portable device including the FIFO can operate without recharging. A further disadvantage of these transitions is that devices responsive to the FIFO output may not have adequate xe2x80x9chold timexe2x80x9d to handle them.
It is, accordingly, an object of the present invention to provide a new and improved FIFO apparatus and method of operating same.
Another object of the invention is to provide a new and improved FIFO and method of operating same such that there is a reduction in power consumed by the FIFO and apparatus responsive to the FIFO output.
A further object of the invention is to provide a new and improved method of and apparatus for reducing the number of signal transitions at the output of a FIFO so there is a reduction in power consumed by the FIFO and circuits responsive to the FIFO output.
In accordance with one aspect of the present invention, the foregoing objects are achieved by operating a first in first out computer type device having N storage stages between an input and output and which is responsive to read and write commands for entries to be read from and written into the computer device by controlling the output so no transition occurs thereon in response to only one of the stages of the device having an input stored therein when a read command signal is supplied to the device exclusively of a write command. Thereby, the output remains at the same value it had immediately prior to the read command signal being supplied to the device.
In an embodiment wherein a RAM based FIFO is employed, contents of read and write pointers for entries in the N stages are controlled so the output remains at the same value it had immediately prior to the read command signal being supplied to the device. In a first embodiment, the control includes decrementing the contents of the write pointer by one without changing the contents of the read pointer. In a second embodiment, the control includes loading the write pointer with the contents of the read pointer.
The foregoing objects are also achieved by preventing transitions from occurring at the computer device output when a command for erasing, i.e. flushing, all entries in the device is supplied thereto. In this arrangement, the control also includes loading the write pointer with the contents of the read pointer. By loading the write pointer with the contents of the read pointer, the FIFO output is maintained static.
In accordance with another aspect of the invention, the foregoing objects are achieved by providing a controlled first in-first out register having N register stages for storing digital words, an input bus responsive to input words and an output bus on which are derived output words. A write pointer responsive to a write command controls coupling of words from the input bus to a designated one of the N stages. A read pointer responsive to a read command controls coupling of words from a designated on of the N stages to the output bus. A controller for the write and read pointers causes the first word supplied to the input bus to be the first word supplied to the output bus so that transitions normally occur on the output bus in response to read and write commands. The controller prevents transitions on the output bus in response to (1) only one stage storing a word at the time the read pointer is supplied with a read command without the write pointer being supplied with a write command and (ii) an erase command being simultaneously supplied to both the read and write pointers so both pointers are reset to an empty state.
Preferably, the controller includes a counter responsive to read and write commands for registering the number of stages storing words and the pointers are synchronously activated in response to transitions of a clock source.
The above and still further objects, features and advantages of the present invention will become apparent upon consideration of the following detailed descriptions of specific embodiments thereof, especially when taken in conjunction with the accompanying drawings.